A simple example will be used to illustrate how a regular von Neumann architecture processor and memory is converted to the modified von Neumann architecture.
This simple regular von Neumann architecture processor will have only one instruction, but it will be suitable for moving data around, doing table lookups, and branching.
The 256-bit instruction will be:
MISCELLANEOUS, NEXT ADDRESS, TO ADDRESS, FROM ADDRESS 64 BITS 64 BITS 64 BITS 64 BITS
The 'MISCELLANEOUS' bits are:
0...0, R4,R3,R2,R1,R0,M31...M0 27 5 32 UNUSED ROTATE MASK
The instruction moves a 32-bit word from the 'FROM ADDRESS' to the 'TO ADDRESS,' then branches always to the 'NEXT ADDRESS.'
If the 32 mask bits, M31...M0 are all 1, then a whole 32-bit word is copied. If only some mask bits are 1, then only those bits are written to. The bits with mask bits with value 0 are not changed.
R4, R3, R2, R1, and R0 is a binary number and indicates the number of bits the 'from data' is rotated to the left before it is copied into the 'to data.' The 'from data' is the data at the 'FROM ADDRESS.' The 'to data' is the data at the 'TO ADDRESS.' The 'from data' is not changed in memory. This is how data can be moved from anywhere in memory to anywhere else, even just a few bits.
To do a table lookup an instruction copies the operand into the last bits of the next instruction's 'FROM ADDRESS.' The next instruction's from address points to a table and that address is modified by the operand to point to the correct entry in the table. If there is more than one operand, one instruction for each operand copies an operand into different last bits of a following instruction's from address.
To branch, a branch address is looked up in a table using the flag as the operand. The branch address is copied into the 'NEXT ADDRESS' of the following instruction.