When converted to the modified von Neumann architecture, the instruction becomes:

MISCELLANEOUS, NEXT ADDRESS, TO ADDRESS, FROM ADDRESS
  64 BITS        64 BITS       64 BITS     64 BITS

The 'MISCELLANEOUS' bits are:

0...0, FL3,FL2,FL1,FL0,FF1,FF0,T,C,S2,S1,S0,R4,R3,R2,R1,R0,M31...M0
  16          4           2    1 1     3           5          32
OPCODE   FLAG NUMBER   FLAG FTN      STEP       ROTATE       MASK

Basic Registers on Bus Architecture

An example of the registers on bus architecture is shown below.

basic registers on bus architecture

The basic registers on bus architecture computer is almost a finite state machine. For instance, if the 'Processor and Memory' was replaced by an increment circuit, the circuit would be a counter, a finite state machine. If the incrementer is replaced by a 'Processor and Memory circuit,' then the processor and memory circuit updates registers, which are in latch 1 and latch 4, to do an instruction step and the whole circuit is a modified von Neumann architecture computer.

The clock that controls the buffers, latches (on the bus) and memory is not shown. It is not quite a regular finite state machine because data can move from latch 1 to the memory in the block of logic comprised of the processor and memory.

The block of logic in the diagram above is labeled 'processor and memory.' However, the registers are not in the processor, though the logic unit (rotate and mask logic) is. The register values are stored in 'latch 1' (or 'latch 4').

'Latch 1' holds 256 bits and so can hold the entire instruction. 'Latch 4' also holds 256 bits and so can hold the entire instruction.

The arrows are just buffers. The arrows point in the direction the data flows. When a buffer is enabled, data can reach the following latch.

For now, An instruction is done in 4 steps (passes around the finite state machine).

For now, we will ignore the 'OPCODE,' which is 16 zeroes. We will also ignore the four bits of the flag number FL3...FL0 (which are all 0 for now). We will also ignore the two flag function ('FLAG FTN') bits which are also 0. 'T' ('Termintate') and 'C' ('Create') will also be ignored for now and are also 0 for now.

'S2' is 0 for now and 'S1' and 'S0' tell which step of the instruction is being done now (on this pass).

S1=0, S0=0 means that step 0 (copy 32 bits from 'FROM ADDRESS' to register 'FROM DATA' (the right 32 bits originally containing 'FROM ADDRESS')) is done on this pass.

S1=0, S0=1 means that step 1 (copy 32 bits from 'TO ADDRESS' to register 'TO DATA' (the left 32 bits originally containing 'FROM ADDRESS')) is done on this pass.

S1=1, S0=0 means that step 2 (copy the result of 'rotate and mask' in the 'TO DATA' and 'FROM DATA' registers to a 32-bit latch in the memory) is done on this pass.

S1=1, S0=1 means that step 3 (fetch the next instruction from 256 bits of memory to the state ('LATCH 4')) will be done on this pass. A word of the memory can be 32 or 256 bits.

The ROTATE and MASK instruction bits are as usual.

During each pass through the block of logic (labeled 'processor and memory' in the diagram), a register or latch in memory is updated.

That's all there is to this basic modified von Neumann architecture computer. It runs the same machine code as the regular von Neumann architecture computer with the same results and uses almost the same circuitry arranged in a slightly different way.


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