PROCESSOR

Four-Bit Memory

Four-Bit Memory

The circuit above shows a memory with four data wires (D3, D2, D1, and D0) and four address wires (A3, A2, A1, and A0). Because there are four address wires, there are sixteen possible latch addresses: 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, and 1111. Only two latches, 0000 and 1111, are shown. The rest are implied by the gap in the circuit diagram.

Two Memories Connected

Two Memories Connected

The circuit diagram above shows a memory with four address wires on the bottom connected with a memory with three address wires on the top. Room has been left in the top memory for additional circuitry later. The two memories share data wires D3, D2, D1, and D0. The three-address-wire memory has address wires RA2, RA1, and RA0, clear wire CLR, and enable wire ENR. In the top memory, the latches are called registers and the address wires are called RA2 for Register Address 2, etc. CLR stands for CLear Register. ENR stands for ENable Register.

Because both memories share data wires D3, D2, D1, and D0, data can be copied from a latch of the bottom memory to a register of the top memory or from a register to a latch.

To copy data from a latch to a register, first select the register with register address keys RA2, RA1, and RA0. Second, temporarily press the CLR key to clear the register loops to all 0's. Third, select the latch address with address keys A3, A2, A1, and A0 (while continuing to select the register with RA2, RA1, and RA0). Fourth, temporarily press the enable keys, ENR and EN, to connect the selected register loops and the selected latch loops to the data wires D3, D2, D1, and D0.

Similarly, to copy data from a register to a latch, first select the latch with address keys A3, A2, A1, and A0. Second, temporarily press the clear key, CL (not CLR), to clear the latch. Third, select the register with register address keys RA2, RA1, and RA0. Fourth, temporarily press the enable keys, ENR and EN. This connects the register and latch loops to the data bus wires, D3, D2, D1, and D0, and, thereby, to each other.


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