The timing diagram that follows, as well as the explanation that follows, tells the order in which to press the keys to execute an instruction with the circuit in the diagram above. Look at the timing diagram below and the circuit above as you read about each step. The following nine steps are tedious, but try to get through them or, at least, study step 1 and read through the rest.
1. The first step in executing an instruction is to copy the value in latch 0000 to register 111. Latch 0000 holds the address of the instruction to be executed. To copy the contents of latch 0000 to register 111, the following is done.
First, RA2 is pressed (gets set to 1), RA1 gets 1, and RA0 gets 1. This selects register 111, the instruction address register. SAF, SAT, and SAI are each set to 0 (not pressed), which selects latch 0000. (This will become clear later.) Then, CLR (CLear Register) is temporarily pressed to clear register 111. Then ENM (ENable Memory) and ENR (ENable Register) are temporarily pressed. When ENM and ENR are pressed, the loops of both latch 0000 and register 111 are connected to the data bus. Therefore, the values in latch 0000 can flow to the loops of (just cleared) register 111 causing register 111 to have the same values as latch 0000. Register 111 then (also) holds the address of the instruction to be executed next.
2. The second step in executing an instruction is to copy the first word (four bits) of the instruction to register 101, the 'from address register,' because the first four bits (word) of an instruction are the address from which the data will be copied. RA0 and RA2 are pressed and RA1 is released to select register 101. Key SAI, for Select Address of Instruction, is pressed, routing the left two bits of register 111 to the address wires, A3 and A2. Pressing key SAI also routes the values of SA1 (Select Address bit 1) and SA0 (Select Address bit 0) to A1 and A0 of the memory. SA1 and SA0 are not pressed, so A1 and A0 get 0. Next, CLR is temporarily pressed, thereby clearing register 101. Next, ENR and ENM are temporarily pressed, connecting to data bus register 101 and the first latch (whose address ends in 00) of the instruction to be executed. Thus the first word of the instruction is copied to latch 101.
3. Third, the second word of the instruction is copied to 'to address register 110.' This is done by pressing RA2, pressing RA1, and not pressing RA0. Also SAI is pressed, SA1 (Select Address bit 1) is not pressed, and SA0 is pressed. Then CLR is temporarily pressed to clear register 110. Then ENM and ENR are temporarily pressed to copy the contents of the second word (4 bits) of the instruction to register 110.
4. Fourth, the third word of the instruction is copied to 'mask register 010.' This is done by not pressing RA2, pressing RA1, and not pressing RA0. Also SAI (Select Address of Instruction) is pressed, SA1 is pressed, and SA0 is not pressed. Then CLR is temporarily pressed to clear register 010. Then ENM and ENR are temporarily pressed to copy the contents of the third word (4 bits) of the instruction to register 010.
5. Fifth, the fourth word of the instruction is copied to 'next/rotate register 100.' This is done by pressing RA2, not pressing RA1, and not pressing RA0. Also SAI is pressed, SA1 is pressed, and SA0 is pressed. Then CLR is temporarily pressed to clear register 100. Then ENM and ENR are temporarily pressed to copy the contents of the fourth word (4 bits) of the instruction to register 100.
6. Sixth, RA2, RA1, and RA0 are not pressed to select register 000, the 'from data register.' SAF (Select Address of From data) is pressed to route the address in 'from address register 101' to the memory's address wires A3, A2, A1, and A0. CLR is then temporarily pressed to clear register 000. Next, ENM and ENR are temporarily pressed to copy the contents of memory pointed to by 'from address register 101' to 'from data register 000.'
7. Seventh, RA2 is not pressed, RA1 is pressed, and RA0 is pressed to select 'to data register 011.' SAT (Select Address of To data) is pressed to route the address in ‘to address register 110’ to the memory's address wires A3, A2, A1, and A0. CLR is then temporarily pressed to clear register 011. Next, ENM and ENR are temporarily pressed to copy the contents of memory pointed to by 'to address register 110' to 'to data register 011.'
8. Eighth, RA2 is not pressed, RA1 is not pressed, and RA0 is pressed to select 'back data register 001.' SAT is pressed to route the address in 'to address register 110' to the memory's address wires, A3, A2, A1, and A0. Next, CLM (CLear Memory, not CLR, CLear Register) is temporarily pressed to clear the latch in memory pointed to by 'to address register 110.' ENR and ENM are then temporarily pressed to copy some rotated bits of 'from data register 000' and not rotated bits of 'to data register 011' to the address in memory pointed to by 'to address register 110.' If the rightmost bit of 'next/rotate register 100' is 1, then the from data is rotated 1 bit left. If the second-to-rightmost bit of 'next/rotate register 100' is 1, then the from data is rotated an additional 2 bits left. If a bit of 'mask register 010' is 0, then the corresponding bit of 'to data register 011' is copied back to memory. However, if a bit of 'mask register 010' is 1, then the corresponding rotated bit of 'from data register 000' is copied back to memory. Notice that because CLM was pressed instead of CLR, a latch of memory was cleared and copied to instead of a register.
9. Ninth, RA2 is pressed, RA1 is not pressed, and RA0 is not pressed to select 'next/rotate register 100.' SAI, SAF, and SAT are not pressed, so no address goes to the memory, so latch 0000 is selected. Next, CLM (not CLR) is temporarily pressed to clear latch 0000 in memory. ENR and ENM are then temporarily pressed to copy the data in 'next/rotate register 100' to latch 0000 in memory. This prepares for the next instruction. Notice, again, that because CLM was pressed instead of CLR, a latch of memory was cleared and copied to instead of a register.
