Next, we want to change the computer again to allow 64 address bits without increasing the size of the state from 256 bits. The new 256-bit instruction will be:

MISCELANEOUS, NEXT ADDRESS, TO ADDRESS, FROM ADDRESS
  64 BITS       64 BITS       64 BITS     64 BITS

The 'MISCELLANEOUS' bits are:

0...0, FL3,FL2,FL1,FL0,FF1,FF0,T,C,S2,S1,S0,R4,R3,R2,R1,R0,M31...M0
  16          4           2    1 1     3           5          32
OPCODE   FLAG NUMBER   FLAG FTN      STEP       ROTATE       MASK

For now, we will ignore the 'OPCODE,' which is 16 zeroes. We will also ignore the four bits of the flag number FL3...FL0 (which are all 0 for now). We will also ignore the two flag function ('FLAG FTN') bits which are also 0. 'T' ('Termintate') and 'C' ('Create') will also be ignored from now and are also 0 for now.

'S2' is 0 for now and 'S1' and 'S0' tell which step of the instruction is being done now (on this pass).

S1=0, S0=0 means that step 0 (copy 32 bits from 'FROM ADDRESS' to register 'FROM DATA' (the right 32 bits originally containing 'FROM ADDRESS')) is done on this pass.

S1=0, S0=1 means that step 1 (copy 32 bits from 'TO ADDRESS' to register 'TO DATA' (the left 32 bits originally containing 'FROM ADDRESS')) is done on this pass.

S1=1, S0=0 means that step 2 (copy the result of 'rotate and mask' in the 'TO DATA' and 'FROM DATA' registers to a 32-bit latch in the memory) is done on this pass.

S1=1, S0=1 means that step 3 (fetch the next instruction from 256 bits of memory to the state ('LATCH 4')) will be done on this pass.

The ROTATE and MASK instruction bits are as usual.